1. Field of the Invention
The present invention relates to solid-state imaging devices and, more particularly, to a solid-state imaging device in which the pixel density is increased, the power consumption is reduced, and the light leakage is reduced.
2. Description of the Related Art
Currently, solid-state imaging devices are widely used in video cameras, still cameras, and so forth. Improvements in performance of solid-state imaging devices, such as an increase in the pixel density, an increase in the resolution, a reduction in mixing of colors in color imaging, and an increase in the sensitivity, are constantly demanded. To meet these demands, technological innovations have been made in order to achieve a higher resolution in solid-state imaging devices by increasing the pixel density or the like.
FIG. 9A and FIG. 9B illustrate a solid-state imaging device according to a known example.
FIG. 9A is a diagram illustrating a cross-sectional structure of a solid-state imaging device according to a known example in which one pixel is formed in one island-shaped semiconductor (see, for example, International Publication No. 2009/034623). As illustrated in FIG. 9A, in an island-shaped semiconductor 100 that constitutes this pixel, a signal line N+ region 102 (hereinafter, an “N+ region” indicates a semiconductor region containing a donor impurity in large amounts) is formed on a substrate 101. On this signal line N+ region 102, a P region 103 (hereinafter, a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed. At an outer periphery portion of this P region 103, an insulating layer 104 is formed. A gate conductor layer 105 is formed with this insulating layer 104 interposing. At the outer periphery portion of the P region 103 above this gate conductor layer 105, an N region (hereinafter, a semiconductor region containing a donor impurity is referred to as an “N region”) 106 is formed. On this N region 106 and the P region 103, a P+ region (hereinafter, a semiconductor region containing an acceptor impurity in large amounts is referred to as a “P+ region”) 107 is formed. This P+ region 107 is connected to a pixel selection line conductor layer 108. The above-described insulating layer 104 is formed so as to be continuous and surround the outer periphery portion of the island-shaped semiconductor 100. Similarly to this insulating layer 104, the gate conductor layer 105 is also formed so as to be continuous and surround the outer periphery portion of the island-shaped semiconductor 100.
In this solid-state imaging device, the P region 103 and the N region 106 constitute a photodiode region in the island-shaped semiconductor 100. When light is incident from the P+ region 107 side in the island-shaped semiconductor 100, signal charges (free electrons in this case) are generated at a photoelectric conversion region of the photodiode region. These signal charges are then accumulated mainly in the N region 106 of the photodiode region.
Also, in the island-shaped semiconductor 100, a junction field-effect transistor is formed in which this N region 106 serves as a gate, the P+ region 107 serves as a source, and the P region 103 in the vicinity of the signal line N+ region 102 serves as a drain. In this solid-state imaging device, a drain-source current (an output signal) of the junction field-effect transistor changes in accordance with the amount of signal charges accumulated in the N region 106, and the drain-source current is output as a signal output via the signal N+ region 102.
Furthermore, in the island-shaped semiconductor 100, a reset MOS transistor is formed in which the N region 106 of the photodiode region serves as a source, the gate conductor layer 105 serves as a reset gate, the signal line N+ region 102 serves as a drain, and the P region 103 between the N region 106 and the signal line N+ region 102 serves as a channel (hereinafter, this gate conductor layer 105 is referred to as a “reset gate conductor layer”). In this solid-state imaging device, signal charges accumulated in this N region 106 are discharged to the signal line N+ region 102 as a result of application of an ON voltage (a high-level voltage) to the reset gate conductor layer 105 of the reset MOS transistor.
Here, it is assumed that the “high-level voltage” indicates a higher-level positive voltage in the case where signal charges are free electrons and a “low-level voltage” used hereinafter indicates a voltage lower than this “high-level voltage”. On the other hand, it is assumed that, in the case where signal charges are positive holes, the “high-level voltage” indicates a lower-level negative voltage and the “low-level voltage” indicates a voltage that is closer to 0 V than the “high-level voltage”.
An imaging operation of this solid-state imaging device is constituted by a signal charge accumulating operation, a signal charge reading operation, and a signal charge discharging operation. In the signal charge accumulating operation, signal charges generated at the photoelectric conversion region (the photodiode region) by light that is incident from the upper surface of the island-shaped semiconductor 100 are accumulated in the N region 106 in a state in which a ground voltage (=0 V) is applied to the signal line N+ region 102, the reset gate conductor layer 105, and the P+ region 107. In the signal charge reading operation, a source-drain current of the junction field-effect transistor modulated based on a potential of the N region 106 that changes in accordance with the amount of accumulated signal charges is read out as a signal current in a state in which the ground voltage is applied to the signal line N+ region 102 and the reset gate conductor layer 105 and a positive voltage is applied to the P+ region 107. In the resetting operation, the signal charges accumulated in the N region 106 are discharged to the signal line N+ region 102 in a state in which the ground voltage is applied to the P+ region 107 and a positive voltage is applied to the reset gate conductor layer 105 and the signal line N+ region 102 after this signal charge reading operation.
FIG. 9B is a schematic plan view of the solid-state imaging device according to the known example. The solid-state imaging device includes a pixel region in which island-shaped semiconductors P11 to P33 (each of which corresponds to the island-shaped semiconductor 100 illustrated in FIG. 9A) each of which constitutes a pixel are two-dimensionally arranged, and driving and output circuits in the vicinity of this pixel region. The cross-sectional structure taken along a line F-F′ in FIG. 9B is illustrated in FIG. 9A. On signal line N+ regions 102a, 102b, and 102c (each of which corresponds to the signal line N+ region 102 in FIG. 9A), the corresponding island-shaped semiconductors P11 to P33 constituting pixels are formed. Pixel selection line conductor layers 108a, 108b, and 108c (each of which corresponds to the pixel selection line conductor layer 108 in FIG. 9A) are formed for corresponding horizontal lines of these island-shaped semiconductors P11 to P33 so as to be continuous and are connected to a pixel selection line vertical scanning circuit 110 provided in the vicinity of the pixel region. Similarly to this, reset gate conductor layers 105a, 105b, and 105c (each of which corresponds to the gate conductor layer 105 in FIG. 9A) are formed for corresponding horizontal lines of the island-shaped semiconductors P11 to P33 constituting pixels so as to be continuous and are connected to a reset line vertical scanning circuit 112 provided in the vicinity of the pixel region. Lower portions of the signal line N+ regions 102a, 102b, and 102c are connected to switch MOS transistors 115a, 115b, and 115c, respectively. Gates of the individual switch MOS transistors 115a, 115b, and 115c are connected to a signal line horizontal scanning circuit 116. Drains of the individual switch MOS transistors 115a, 115b, and 115c are connected to an output circuit 117. Upper portions of the signal line N+ regions 102a, 102b, and 102c are connected to switch circuits 118a, 118b, and 118c, respectively. To the switch circuits 118a, 118b, and 118c, the ground voltage (=0 V) is applied during the signal charge accumulating operation, a floating voltage is applied during the signal charge reading operation, and a high-level voltage Vr for turning on resetting is applied during the signal charge discharging operation.
The signal charge accumulating operation is performed in a state in which the ground voltage is applied to the signal line N+ regions 102a, 102b, and 102c, a low-level voltage for turning off resetting is applied to the reset gate conductor layers 105a, 105b, and 105c, and the ground voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c. 
The signal charge reading operation is performed in the following manner. Source-drain currents of junction field-effect transistors of pixels subjected to reading are loaded to the output circuit 117 in a state in which a low-level voltage for turning off resetting is applied to the reset gate conductor layers 105a, 105b, and 105c, a high-level voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c of pixels from which signal charges are read out, an ON voltage (a high-level voltage) is applied to gates of the switch MOS transistors 115a, 115b, and 115c connected to the signal line N+ regions 102a, 102b, and 102c of pixels from which signal charges are read out, voltages at the output terminals of the switch circuits 118a, 118b, and 118c are a floating voltage, and a voltage at an input terminal of the output circuit 117 is a low-level voltage.
Furthermore, the signal charge discharging operation is performed in the following manner. In a state in which all the pixel selection line conductor layers 108a, 108b, and 108c have the ground voltage and all the switch MOS transistors 115a, 115b, and 115c are off, a high-level voltage for turning on resetting is applied to the reset gate conductor layers 105a, 105b, and 105c that are connected to pixels, among the island-shaped semiconductors P11 to P33, from which accumulated signal charges are discharged. As a result of the application, the output terminals of the switch circuits 118a, 118b, and 118c come to have the high-level voltage Vr for turning on resetting.
As illustrated in FIG. 9A, a height of the island-shaped semiconductor 100 is determined mainly by a height Ld of the N layer 106 of the photodiode. Here, light is incident from the upper surface of the P+ layer 107 of the island-shaped semiconductor 100. The generation rate of signal charges generated by this incident light has a characteristic that the generation rate exponentially decreases with respect to a depth Si from the upper surface of the P+ layer 107. In order to efficiently extract signal charges that contribute to the sensitivity in solid-state imaging devices that detect visible light, a photoelectric conversion region needs to have a depth of 2.5 to 3 μm (see, for example, G. Agranov, R. Mauritzson, J. Ladd, A. Dokoutchaev, X. Fan, X. Li, Z. Yin, R. Johnson, V. Lenchenkov, S. Nagaraja, W. Gazeley, J. Bai, H. Lee, and Yoshinori Takizawa, “Reduction in Pixel Size and Characteristic Comparison of CMOS Image Sensor (CMOS Imeeji Sensa no Gaso Saizu Shukushou to Tokusei Hikaku)”, ITE Technical Report, Vol. 33, No. 38, pp. 9-12 (September 2009)). For this reason, the height Ld of the N layer 106 of the photoelectric conversion photodiode needs to be at least 2.5 to 3 μm. The reset gate conductor layer 105 is formed below this N layer 106. Even the reset gate conductor layer 105 having a height of, for example, 0.1 μm successfully performs an expected operation of the solid-state imaging device. Thus, the reset gate conductor layer 105 is formed at a region near the bottom portion of the island-shaped semiconductor 100.
As illustrated in FIG. 9B, because the reset gate conductor layers 105a, 105b, and 105c are formed independently for each line, the reset gate conductor layers 105a, 105b, and 105c need to be formed at the bottom portions of the island-shaped semiconductors P11 to P33 in which the height of 2.5 to 3 μm is ensured. As integration of pixels increases, finer patterning is needed in formation of these reset gate conductor layers 105a, 105b, and 105c, which makes it difficult to fabricate this solid-state imaging device.
FIG. 10A and FIG. 10B are a schematic diagram of a pixel of a CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging device and a diagram of changes in operation potentials, respectively. FIG. 10A is a schematic diagram of a pixel as illustrated in FIG. 1 of H. Takahashi, M. Kinoshita, K. Morita, T. Shirai, T. Sato, T Kimura, H. Yuzurihara, S. Inoue, and S. Matsumoto, “A 3.9-μm Pixel Pitch VGA Format 10-b Digital Output CMOS Image Sensor With 1.5 Transistor/Pixel”, IEEE Journal of Solid-State Circuit, Vo. 39, No. 12, pp. 2417-2425 (2004). In a region A enclosed by a dotted line in FIG. 10A, one pixel is formed. In this figure, an N region 121 that constitutes a photodiode and a P+ region 122 on this N region 121 are formed in a P region 120. A gate insulating layer 124 is formed on the P region 120. On this gate insulating layer 124, a transfer electrode ΦT is formed so as to be adjacent to the N region 121. An N+ region 123 is formed on a surface of the P region 120 so as to be adjacent to this transfer electrode ΦT. A potential of the P+ region 122 is fixed to a ground potential. The P region 120 and the N region 121 constitute a photodiode. With this configuration, a transfer MOS transistor M1 is formed in which the N region 121 serves as a source, the N+ region 123 serves as a drain, and the transfer electrode ΦT serves as a gate. A source of a reset MOS transistor M2 and a gate of an amplifying MOS transistor M3 are connected to the N+ region 123. A drain of the reset MOS transistor M2 and a source of the amplifying MOS transistor M3 are connected to a power voltage line VDD. Also, a source of a column selecting MOS transistor M4 is connected to a drain of the amplifying MOS transistor M3, whereas a drain of the column selecting MOS transistor M4 is connected to a signal line 125.
In this pixel, light that is incident from the P+ region 122 side undergoes photoelectric conversion at a photodiode region to generate signal charges (free electrons in this case). These signal charges are accumulated in the N region 121. An ON voltage (a high-level voltage) is then applied to the transfer electrode ΦT, and consequently the signal charges accumulated in the N region 121 are transferred to the N+ region 123. As a result of such an operation, a gate electrode potential of the amplifying MOS transistor M3 changes in accordance with the amount of signal charges. In response to application of an ON voltage (a high-level voltage) to a gate electrode ΦS of the column selecting MOS transistor M4, a signal current modulated based on the gate electrode potential of the amplifying MOS transistor M3 flows from the power voltage line VDD to the signal line 125 via the amplifying MOS transistor M3 and the column selecting MOS transistor M4, and this signal current is read out as a pixel signal. In response to application of an ON voltage (a high-level voltage) to a gate electrode ΦR of the reset MOS transistor M2, the signal charges existing in the N+ region 123 are discharged to the power voltage line VDD.
FIG. 10B is a diagram of changes in potential distributions in the photodiode N region 121, the transfer MOS transistor M1, and the reset MOS transistor M2 (see, for example, FIG. 2 of P. P. K. Lee, R. C. Gee, R. M. Guidash, T-H. Lee, and E. R. Fossum, “An Active Pixel Sensor Fabricated Using CMOS/CCD Process Technology” in Program IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, (1995)). FIG. 10B (a) is a cross-sectional diagram of the photodiode constituted by the P region 120 and the N region 121, the transfer MOS transistor M1 region, and the reset MOS transistor M2 region. The N+ region 123, which constitutes a floating diode FD, is adjacent to a gate electrode Tx (which corresponds to the transfer electrode ΦT in FIG. 10A) of the transfer MOS transistor M1. A reset electrode RST (which corresponds to the gate electrode ΦR of the reset MOS transistor M2 in FIG. 10A) of the reset MOS transistor M2 is adjacent to this N+ region 123. An N+ region 126, which serves as the drain of the reset MOS transistor M2 connected to the power voltage line VDD, is formed on the surface of the P region 120 so as to be adjacent to this reset electrode RST.
FIG. 10B (b) illustrates a potential distribution along a line G-G′ in FIG. 10B (a) during the signal charge accumulating operation. A solid line represents the bottom of the potential of each region, whereas a hatched part represents charges (free electrons in this case). The N region 121 contains accumulated signal charges 128. The N+ regions 123 and 126 contain many charges 129a and 129b (free electrons in this case). An OFF voltage (a low-level voltage) is applied to the transfer electrode Tx and the reset electrode RST so as to prevent the accumulated signal charges 128 from being transferred to the N+ region 123 and the N+ region 126 serving as the drain of the reset MOS transistor M2 from the photodiode N region 121.
FIG. 10B (c) illustrates a potential distribution when the signal charges 128 accumulated in the N region 121 of the photodiode is transferred to the N+ region 123. This transfer is performed by applying an ON voltage (a high-level voltage) to the transfer electrode Tx. The accumulated signal charges 128 are transferred from the N region 121 to the N+ region 123 through a surface layer of the P region 123 located below the transfer electrode Tx. During this transfer, signal charges 130a in the N region 121 decrease and signal charges 130c in the N+ region 123 increase as illustrated in FIG. 10B (c). At the time when the signal charges 130a and 130b no longer exist, this signal charge transferring operation ends. The potential at the gate electrode of the amplifying MOS transistor M3 connected to the N+ region 123 changes as a result of the transfer of the signal charges 128 to the N+ region 123. In accordance with the amount of this potential change, a signal current that flows through the signal line 125 changes and is read out as a signal output during the signal charge reading operation.
After this signal charge reading operation, an ON voltage (a high-level voltage) is applied to the gate electrode RST of the reset MOS transistor M2 so as to discharge the signal charges 130c in the floating diode N+ region 123 to the N+ region 126, which is the drain of the reset MOS transistor M2, as illustrated in FIG. 10B (d). During this signal charge discharging operation, the potential of the N+ region 123 is reset and becomes equal to a potential 131 of the surface layer of the P region 120 located below the reset electrode RST.
As described above, the transfer MOS transistor M1 and the reset MOS transistor M2 are needed in each pixel in the solid-state imaging device having the pixels illustrated in FIG. 10A. The presence of such transfer MOS transistor M1 and reset MOS transistor M2 leads to a decrease in the pixel integration.
Referring to FIG. 11A and FIG. 11B, a signal charge discharging operation in a CCD (Charge Coupled Device) solid-state imaging device will be described below. FIG. 11A illustrates a cross-sectional structure of one pixel of a CCD solid-state imaging device (see, for example, FIG. 1 of I. Murakami, T. Nakano, K. Hatano, Y. Nakashiba, M. Furumiya, T. Nagata, T. Kawasaki, H. Utsumi, S. Uchiya, K. Arai, N. Mutoh, A. Kohno, N. Teranishi, and Y. Hokari, “Technologies to Improve Photo-Sensitivity and Reduce VOD Shutter Voltage for CCD Image Sensors”, IEEE Transactions on Electron Devices, Vol. 47, No. 8, pp. 1566-1572 (2000)). A P region well 141 is formed on an N region substrate 140. On this P region well 141, an N region 142 is formed. The P region well 141 and the N region 142 constitute a photodiode portion. On this N region 142, a P+ region 143 is formed. This P+ region 143 is set to have a ground voltage (=0 V). A CCD portion is formed to be adjacent to the photodiode portion. On a surface of the P region well 141 in the CCD portion, a P region 144 and an N region 145 are formed which serve as a channel of this CCD portion. On a surface layer of the P region well 141 between the channel of this CCD portion and the photodiode N region 142, a transfer channel 146 for transferring signal charges accumulated in the photodiode portion to the N region 145 of the channel of the CCD portion is formed. On the P+ region 143, the transfer channel 146, and the N region 145 of the channel of the CCD portion, an insulating film 147 is formed. Inside the insulating film 147 in the CCD portion, a CCD transfer electrode 148 is formed, above which a light-shielding metal layer 149 is formed so as to cover the CCD portion. Above the photodiode portion and the CCD portion, a transparent resin microlens 150 is formed. One pixel is constituted by the photodiode portion and the CCD portion illustrated in FIG. 11A. These pixels are two dimensionally arranged all over a pixel region of the CCD solid-state imaging device. The N region substrate 140 and the P region well 141 are formed so as to be continuous all over the pixel region.
An operation of transferring signal charges accumulated in the above-described photodiode portion is performed by applying a certain voltage to the CCD transfer electrode 148. The signal charge discharging operation is performed by applying a high-level voltage to the N region substrate 140 after the signal charge accumulation operation to discharge the signal charges accumulated in the N region 142 to the N region substrate 140. Each of the signal charge accumulating operation and the signal charge discharging operation is simultaneously performed in the pixels in the entire pixel region and the signal charge accumulating period is altered, whereby the timing of a shutter operation can be changed. This shutter operation is called an electronic shutter.
FIG. 11B illustrates potential distributions at the time of discharging of signal charges along a line H-H′ in FIG. 11A (see FIG. 14 of I. Murakami, T. Nakano, K. Hatano, Y. Nakashiba, M. Furumiya, T. Nagata, T. Kawasaki, H. Utsumi, S. Uchiya, K. Arai, N. Mutoh, A. Kohno, N. Teranishi, and Y. Hokari, “Technologies to Improve Photo-Sensitivity and Reduce VOD Shutter Voltage for CCD Image Sensors”, IEEE Transactions on Electron Devices, Vol. 47, No. 8, pp. 1566-1572 (2000)). A potential of the P+ region 143 is fixed to a ground potential Vs (=0 V). During the signal charge accumulating operation, a potential distribution 151a is obtained in which a low-level voltage VRL is applied to the N region substrate 140. During this operation, signal charges 152a (in this figure, signal charges are represented by “e−” described in P. P. K Lee, R. C. Gee, R. M. Guidash, T-H. Lee, and E. R. Fossum, “An Active Pixel Sensor Fabricated Using CMOS/CCD Process Technology” in Program IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, (1995), and are equivalent to the signal charges 128, 130a, 130b, and 130c illustrated as the hatched parts in FIG. 10B), which are generated by light radiated from the microlens 150 side, are accumulated in a potential well of the N region 142 and the P region well 141. During the signal charge discharging operation, a potential distribution 152b is obtained in which a high-level voltage VRH is applied to the N region substrate 140. The potential deepens towards the N region substrate 140 from the P+ region 143 having the ground potential. In this manner, accumulated signal charges 152b are discharged to the N region substrate 140.
In the above-described signal charge accumulating operation, signal charges generated in the potential well are effective as a signal, whereas signal charges generated in the P region well 141 and the N region substrate 140 that are located below the potential well are ineffective as a signal because they are discharged to the N region substrate 140. As described in International Publication No. 2009/034623, a depth Lph of this potential well is set to be 2.5 to 3 μm to meet the required spectral sensitivity characteristics. Further, it is undesirable that a potential barrier is caused during transfer of the signal charges 151 from the P+ region 143 to the N region substrate 140 in the potential distribution at the time of the signal charge discharging operation. Accordingly, the voltage VRH applied to the N region substrate 140 is set to be 18 to 30 V because the photoelectric conversion region constituted by the N region 142 and the P region well 141 overlaps the signal charge discharging region constituted by the P region well 141 and the N region substrate 140. This voltage is a significantly large value compared with the fact that the operation can be performed by applying a voltage of 2 to 3 V to the reset gate conductor layer 105 and to the gate electrode ΦR of the reset MOS transistor M2 at the time of discharging the signal charges in the solid-state imaging devices illustrated in FIGS. 9A and 10A. Due to this high voltage, the power consumption of the CCD solid-state imaging device increases.
The solid-state imaging devices illustrated in FIG. 9A and FIG. 10A, which read out pixel signals by using the X-Y address (dot sequential) method and the row address (line sequential) method, are unable to perform the pixel-signal charge reading operation and the pixel-signal-charge discharging operation simultaneously in pixels in the entire pixel region. For this reason, these solid-state imaging devices are unable to perform the signal charge discharging operation (the electronic shutter operation) of the above-described CCD solid-state imaging device. In order to perform this signal charge discharging operation (the electronic shutter operation), the CMOS solid-state imaging device illustrated in FIG. 10A needs to additionally include special transistors as described above (see, for example, K. Yasutomi, T. Tamura, F. Furuta, S. Itho, and S. Kawahito, “A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixel Using Pinned Diodes”, IEEJ Trans. SM, Vol. 129, No. 10, pp. 321-327 (2009)). Addition of such transistors decreases the pixel integration.
In the solid-state imaging device illustrated in FIG. 9A in which one pixel is formed in one island-shaped semiconductor, the height of the island-shaped semiconductor 100 is determined mainly by the height Ld of the N layer 106 of the photodiode. The generation rate of signal charges generated by radiation of light has a characteristic that the generation rate exponentially decreases with respect to the depth Si from the upper surface of the P+ layer 107. In order to efficiently extract signal charges that contribute to the sensitivity in solid-state imaging devices that detect visible light, the photoelectric conversion region needs to have a depth of 2.5 to 3 μm (see, for example, G. Agranov, R. Mauritzson, J. Ladd, A. Dokoutchaev, X. Fan, X. Li, Z. Yin, R. Johnson, V. Lenchenkov, S. Nagaraja, W. Gazeley, J. Bai, H. Lee, and Yoshinori Takizawa, “Reduction in Pixel Size and Characteristic Comparison of CMOS Image Sensor (CMOS Imeeji Sensa no Gaso Saizu Shukushou to Tokusei Hikaku)”, ITE Technical Report, Vol. 33, No. 38, pp. 9-12 (September 2009)). For this reason, the height Ld of the N layer 106 of the photoelectric conversion photodiode needs to be at least 2.5 to 3 μm. The reset gate conductor layer 105 is formed below this N layer 106. Even the reset gate conductor layer 105 having a height of, for example, 0.1 μm successfully operates. Thus, the reset gate conductor layer 105 is formed substantially at the bottom portion of the island-shaped semiconductor 100. As illustrated in FIG. 9B, because the reset gate conductor layers 105a, 105b, and 105c are formed independently for each line, the reset gate conductor layers 105a, 105b, and 105c need to be formed at the bottom portions of the island-shaped semiconductors P11 to P33 having the height of 2.5 to 3 μm. As integration of pixels increases, the presence of such reset gate conductor layers 105a, 105b, and 105c makes it more difficult to fabricate this solid-state imaging device.
The CMOS solid-state imaging device that includes the pixels illustrated in FIG. 10A requires the reset MOS transistor M2 in each pixel. The presence of this reset MOS transistor M2 decreases the pixel integration.
In the CCD solid-state imaging device illustrated in FIG. 11A, the depth Lph of the potential well that accumulates signal charges as illustrated in FIG. 11B is set to be 2.5 to 3 μm to meet the required spectral sensitivity characteristics as disclosed in G. Agranov, R. Mauritzson, J. Ladd, A. Dokoutchaev, X. Fan, X. Li, Z. Yin, R. Johnson, V. Lenchenkov, S. Nagaraja, W. Gazeley, J. Bai, H. Lee, and Yoshinori Takizawa, “Reduction in Pixel Size and Characteristic Comparison of CMOS Image Sensor (CMOS Imeeji Sensa no Gaso Saizu Shukushou to Tokusei Hikaku)”, ITE Technical Report, Vol. 33, No. 38, pp. 9-12 (September 2009). Further, it is required that a potential barrier is not caused during transfer of the signal charges 151 from the P+ region 143 to the N region substrate 140 in the potential distribution at the time of the signal charge discharging operation. Accordingly, the voltage VRH applied to the N region substrate 140 is required to be a high voltage, such as 18 to 30 V. This increases the power consumption of the CCD solid-state imaging device.